============================================================== Guild: wafer.space Community Channel: Information / general / I managed to persuade pdngen to connect After: 07/31/2025 23:59 Before: 09/01/2025 00:00 ============================================================== [08/27/2025 13:19] mole99 [08/27/2025 13:19] mole99 The trick (or problem) is that the DVDD/DVSS pins are all on Metal2, which means the PDN ring will only connect to the pads via Metal2. Metal2 is vertical by default, which means we can only have I/O power/ground cells in the northern or southern I/O row (in the current setup, I hope we can change this). [08/27/2025 13:19] mole99 This example design now runs through the whole flow without any problems, except that netgen LVS fails since the power/ground pins are not yet properly represented in the PNL. [08/27/2025 13:19] mole99 @tnt I think you looked into overriding the preferred directions in pdngen at some point? Did you manage to achieve this? [08/27/2025 13:20] mole99 @htamas I noticed that you have some `CONNECT_POWER_PADS` defines in your code. Did you manage to get the PNL to properly connect the core PDN to the I/O power/ground bondpad pins? [08/27/2025 13:20] mole99 I'm gonna upload this repo soon to the wafer.space GitHub with a WIP PDK so anyone can reproduce this with the LibreLane padring step. [08/27/2025 13:27] 246tnt @Leo Moser (mole99) No, I didn't manage to do it, it's pretty wired down everywhere ... and in the end the IHP guys changed the direction in the tech LEF 😅 [08/27/2025 13:32] mole99 Well, that's one solution 😄 Actually, I think the `add_pdn_ring -connect_to_pads` function should be more flexible. If we have a core ring with Metal5 and Metal4, it should still be able to make all connections with Metal2 and then drop vias. Maybe this function just needs another argument to override this. I'll ask the folks at OpenROAD what they think about this. [08/30/2025 17:23] mole99 I got the power/ground bondpads connected and LVS to match 👏 [08/30/2025 17:24] mole99 @htamas In your padring script, I saw that you used `place_io_terminals` to place the BTerms for the I/O pads, since the bondpads are integrated into the cells (as opposed to IHP): ``` place_io_terminals gf180mcu_fd_io__*/DVSS place_io_terminals gf180mcu_fd_io__*/DVDD ``` It seems that `place_io_terminals` simply promotes the first pin of the specified port to a BTerm. [08/30/2025 17:24] mole99 For the default power/ground pads that would be one of the pins on the side, resulting in this: [08/30/2025 17:24] mole99 {Attachments} 2025-08_media/Bildschirmfoto_vom_2025-08-30_18-29-36-9051A.png [08/30/2025 17:24] mole99 It turns out that the power/ground pads don't even have pins at the bondpad locations, so by default the `place_io_terminals` command cannot work as we want it to work. Therefore, I tried to add a `PAD` port, just like the other I/O pads, which initially seemed to work fine: I could global-connect it to the respective VDD/VSS net. However, PSM would throw an error, because there is no physical connection between PAD and any of the power pins. ``` [18:32:56] ERROR [PSM-0069] Check connectivity failed on VDD. [18:33:07] ERROR [PSM-0069] Check connectivity failed on VSS. ``` [08/30/2025 17:25] mole99 So instead I added another pin to the DVSS/DVDD ports that matches the location of the bondpads (same as PAD) and is listed as the first pin in the LEF file. This way `place_io_terminals` promotes the correct pin to a BTerm. However, instead of: ``` place_io_terminals gf180mcu_fd_io__*/DVSS place_io_terminals gf180mcu_fd_io__*/DVDD ``` We have to write: ``` place_io_terminals gf180mcu_fd_io__dvss*/DVSS place_io_terminals gf180mcu_fd_io__dvdd*/DVDD ``` As otherwise we would still get one BTerm at the side of the power/ground pad. [08/30/2025 17:25] mole99 With this change the PDN is complete: [08/30/2025 17:25] mole99 {Attachments} 2025-08_media/Bildschirmfoto_vom_2025-08-30_19-00-07-96E58.png [08/30/2025 17:25] mole99 PSM is happy: ``` [INFO PSM-0040] All shapes on net VDD are connected. [INFO PSM-0040] All shapes on net VSS are connected. ``` And netgen as well: ``` Final result: Circuits match uniquely. ``` {Reactions} 🎉 [08/30/2025 17:26] mole99 I think that would be reasonable change in the PDK. What do you think @tnt @htamas @Tholin? [08/30/2025 17:37] h.tamas Sounds good to me, thanks for figuring it out. {Reactions} 👍 [08/30/2025 17:40] mole99 Thanks, your script was really helpful! [08/30/2025 17:45] 246tnt @Leo Moser (mole99) ack. [08/30/2025 17:48] tholin Definitely a less scuffed solution than me giving the power/ground IO cells tails. [08/30/2025 17:49] tholin And tricking pdngen into thinking those tails are part of the PDN grid. [08/30/2025 17:54] mole99 Sounds good then. I'll update the LEF view of `gf180mcu_fd_io__dvss` and `gf180mcu_fd_io__dvdd` to add the pin geometry. {Reactions} 👍 ============================================================== Exported 24 message(s) ==============================================================